1. Field of the Invention
The present invention relates to the field of integrated circuits. More particularly, the present invention relates to a method and apparatus for controlling a charge pump of an integrated circuit during power up for rapid initialization.
2. Description of Related Art
Flash electrically erasable programmable read-only memory (EEPROM) and other non-volatile memories are often used in applications, such as portable devices, in which it is particularly desirable to have reduced power consumption. It is also desirable to achieve this reduced power consumption while limiting the increase in latency of operations.
In active mode, the memory is capable of performing memory operations, such as read, program, and erase. Some non-volatile memories implement a standby mode which disables much of the circuitry of the non-volatile memory to reduce power consumption at the cost of increased latency to enter active mode.
Some non-volatile memories also implement a deep powerdown mode in which even more circuitry is disabled for even lower power consumption at the cost of longer latency to enter active mode as compared to standby mode.
During power-up, when the external power supply voltage is ramping to its steady-state voltage, the non-volatile memory may be in standby, deep powerdown or active mode depending on external control signals applied to the non-volatile memory.
Many non-volatile memories use an operating voltage higher than the externally supplied voltage for read operations. The higher operating voltage is split into a positive voltage on one node (approximately 5 volts) and a negative voltage on another node (approximately -5 volts). The first node is used as the read logic power supply and the second node is used as the local block selects power supply in a flash EPROM architecture according to well-known methods. These nodes typically have high capacitance because they are coupled to repeated structures within the memory array. The use of the charge pump to drive these large capacitive nodes to their corresponding operating voltages and maintain these voltages consumes power. The use of a negative charge pump to produce the negative voltage tends to frustrate power conservation in low power mode since negative charge pumps are less efficient than positive charge pumps in some process technologies.
Some non-volatile memories disable the positive and negative charge pumps when in standby or deep powerdown modes to reduce power consumption. These non-volatile memories use relatively expensive three-well processes such that negatively biased nodes are not required in standby or deep powerdown modes. A less expensive two-well process would require that the negatively biased nodes be maintained during standby or deep powerdown modes thereby consuming more power. If the charge pumps are operated at a level sufficient only to maintain the voltage level in the reduced power modes, the latency in returning to active mode may be unacceptably impacted.
What is needed is a method and apparatus to minimize power up time while maintaining low power consumption for non-volatile memories that use negative charge pumps in devices that require a negative voltage be maintained, such as a non-volatile memory produced using a two-well process.